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Communications systems using phase shift keying (PSK) modulation schemes are known. Such systems use the phase of a transmitted/received signal to transmit/receive intelligent data. The transmitted/received signal can be represented as a series of data vectors originating at the origin and having end points at data point values on a circle of an orthogonal system. Each data vector, accordingly, has an in phase component, known as the I coordinate or value of the data vector, and a quadrature component, known as the Q coordinate or value of the data vector. The transmissions from the transmitter of the communications system to a receiver of the communications system are often in the form of bursts of data, particularly in point-to-multipoint communications systems.
A PSK system in which data is represented by n points or vectors on the circle is known as an nPSK system. In nPSK systems there are xe2x80x9cnxe2x80x9d number of (usually equally spaced) data points along the vector circle, each point representing transmitted/received data. I and Q vectors change their relation with each other to control the data sent in nPSK systems. The relationship is referred to as a rotation of the composite phase vector V in an I and Q orthogonal system. This relationship is depicted in FIG. 1.
In QPSK (Quadrature Phase Shift Keying) systems, four data points are used. The I and Q vectors form xe2x80x9csymbolsxe2x80x9d of information, each symbol being one of the four digital states represented by the I and Q vectors, taken as 2 bits and relating to the four points seen on the circle of FIG. 1 and labeled 00, 01, 10, 11. QPSK systems offer an advantage in that the data points are few in number. As such, any phase error in the QPSK receiver causing the vector V to improperly move from position V to V1 of FIG. 1 will have to be substantial before the receiver has difficulty resolving whether it is the data point representing, for example, data state 00 of vector V1 or the data point representing data state 01 of vector V2. This phase error is most often caused by slips and shifts in time of the I and Q at the beginning and ending edges of a symbol period. These slips and shifts are frequently a function of phase errors between the received signal after it has been down converted to an intermediate frequency, IF, and the IF signal used to demodulate the QPSK symbols.
Referring to FIG. 2, there is shown the I and Q signals represented by lines 20 and 25 of a received signal that has been down converted to an intermediate frequency. As shown, the I and Q signals change states in accordance with the data transmitted during each symbol period. As such, the received sinusoidal IF that was used to develop the I (line 20) and the Q (line 25) envelope depicted by line 30, unless it is absolutely phased to the signal used in the modulation of the I and Q signal, will have inaccuracies during the times designated at E and F. This inaccuracy in the envelope will cause phase errors. The higher the ratio between the IF frequency and the I and Q signal transition frequencies, the better the resolution and hence less phase error.
One manner of synthesizing the signal used to demodulate the I and Q signals is to synthesize the demodulating signal using direct digital synthesis (DDS) of the entire IF waveform, keeping the received IF signal and synthesized demodulating signal completely in phase at all times. The present inventors, however, have recognized that such DDS schemes are often quite complicated and costly to implement. As such, they have set forth an nPSK burst communications system and receiver architecture which is less costly to implement than its DDS counterpart while still being highly reliable and accurate. Additionally, the inventors have set forth a clock generator/data decoding circuit that improves the integrity of the received data.
An nPSK communications system is set forth. The communications system includes a transmitter for transmitting phase shift key modulated burst signals, including I and Q components, on a transmission medium. The burst signals include a prefix portion and a data portion. The I and Q components of the prefix portion are maintained at a predetermined relationship during at least a portion of the prefix portion. The communications system also includes a receiver for receiving the phase shift key modulated burst signals from the transmission medium. The receiver includes an IF section for mixing received burst signals to an intermediate frequency signal, the intermediate frequency signal having a phase. The receiver further includes an I-Q demodulator that comprises a demodulator frequency generator for generating a demodulating signal having a frequency equal to or an integer multiple of the intermediate frequency signal to thereby extract the I and Q components of the received burst signals. A phase adjustment circuit, responsive to the I and Q components that are maintained at the predetermined relationship, is used for adjusting the phase of the demodulating signal so that it is substantially in phase with the intermediate frequency signal.
In accordance with a further aspect of the disclosed invention, a receiver for receiving phase shift key modulated signals that are transmitted at a symbol rate in which a circuit for determining the respective states of baseband I and Q signals of the phase shift key modulated signals is set forth. The circuit comprises a transition detector for detecting a state transition of at least one of the baseband I and Q signals and for generating a state transition signal in response to the state transition. A peak detector circuit detects the occurrence of the peak amplitude of at least one of the baseband I and Q signals and generates a peak detected signal in response to occurrence of the peak amplitude. A clock generator circuit generates the symbol clock signal at the symbol rate in response to the state transition signal and the peak detected signal to adjust the phase of the symbol clock signal. An analog-to-digital converter samples each of the baseband I and Q component signals at a predetermined rate to generate a first digital sample output stream from the baseband I component and a second digital sample output stream from the baseband Q component. Each digital data sample of the first digital sample output stream is indicative of a logic state of the baseband I component at a respective sample time and each digital data sample of the second digital sample output stream is indicative of a logic state of the baseband Q component at a respective sample time. The predetermined rate is at least twice the Nyquist frequency of the baseband I and Q component signals. A voter circuit receives the first and second digital data sample streams, and, in response to occurrence of the symbol clock signal, compares a current digital data sample of the first digital data sample output stream to prior and subsequent digital data samples of the first digital data sample output stream to provide an I state signal output and, in response to occurrence of the symbol clock signal, compares a current digital data sample of the second digital data sample output stream to prior and subsequent digital data samples of the second digital data sample output stream to provide a Q state signal output.